1. Field of the Invention
This invention relates generally to a semiconductor device, and, more particularly, to providing a preselected voltage to test or repair the semiconductor device.
2. Description of the Related Art
Modern integrated circuit devices are comprised of millions of semiconductor devices, e.g., transistors, formed above a semiconductor substrate, such as silicon. These devices are very densely packed, i.e., there is little space between them. Similarly, electrically conductive lines/traces may also be formed in the semiconductor substrate. Generally, the lines/traces electrically connect selected semiconductor devices to form circuits capable of performing complex functions. For example, data may be stored in a semiconductor memory device by providing electrical current to a plurality of bit lines and a plurality of word lines that may be electrically coupled to one or more capacitors in the semiconductor memory. In at least some applications, a large number of lines/traces may be required, such that they, too, may be relatively densely packed.
The semiconductor memory may be a dynamic random access memory, a flash memory, and the like. The semiconductor memory typically comprises an array of memory cells, address decoding circuitry for selecting one, or a group, of the memory cells for reading or writing data, sensing circuitry for detecting the digital state of the selected memory cell or memory cells, and input/output lines to receive the sensed data and convey that information out of the semiconductor memory. In many cases, the array of memory cells will be subdivided into several sub-arrays, or subsets of the complete collection of memory cells. For example, a semiconductor memory having 16 megabits (224 bits) of storage capacity, may be divided into 64 sub-arrays, each having 256K (218) memory cells.
Although forming the selected electrical connections may enable the circuits to perform their intended functions, undesirable electrical connections may result in a variety of malfunctions, e.g., short circuit paths may be established. Thus, semiconductor devices such as the capacitors in memory cells and conducting lines such as the input/output lines may generally be electrically isolated. For example, to insure that devices, lines, and/or groups thereof that may form the semiconductor memory are properly isolated, modern semiconductor processing involves the formation of shallow trench isolations (STI) in various regions of the substrate. These shallow trench isolations are typically formed by etching a trench in the semiconductor substrate and, thereafter, filling the trench with an isolation material, e.g., an insulator, such as silicon dioxide, silicon oxynitride, silicon nitride, or other like materials.
However, it may be difficult to completely isolate the devices and/or lines. For example, defects in the semiconductor substrate or in the manufacturing process may form an undesirable conducting path, sometimes referred to as a “stringer,” between the devices and/or lines in the semiconductor memory that may cause the semiconductor memory to malfunction. In one embodiment, a test voltage may be applied to the word lines and/or bit lines to determine how memory cells in the semiconductor memory perform under stress. For example, stringers may be detected and/or repaired by applying the test voltage to the semiconductor memory. But the semiconductor memory may not be able to provide a voltage that is high enough to enable the stringer to be detected and/or repaired. Thus, a margin mode circuit may be used to provide the test voltage.
Traditionally, the test voltage may be applied using a tester 100 that may be located on a semiconductor memory device 105, as shown in FIG. 1. The margin mode circuit in the tester 100 may include a multi-stage pump 110, a clock generator 115, an oscillator 120, and an enable logic 125 that may be used to facilitate the transfer of an external voltage from a memory pad 130 to a semiconductor memory array 140 via a transistor 145. The multi-stage pump 110, the clock generator 115, the oscillator 120, and the enable logic 125 may be coupled to a supply voltage 160 and a low voltage 165. For example, in one embodiment, the supply voltage 160 may be equal to 3 Volts and the low voltage 165 may be equal to ground, i.e. 0 Volts.
To transfer a voltage that is larger than the supply voltage 160 from the memory pad 130 to the semiconductor memory array 140, a gate of the transistor 145 may be coupled to the multi-stage pump 110, which may provide a voltage that may be used to forward bias the transistor 145. For example, if a voltage of 10 Volts is applied to the memory pad 130, the multi-stage pump 110 may provide a voltage equal to 10 Volts plus the threshold voltage of the transistor 145. A typical threshold voltage for the transistor 145 is about 1 Volt. To provide the voltage of about 11 Volts to the transistor 145 using the supply voltage 160, the multi-stage pump 110 may use 4 or 5 multiplying stages (not shown).
The tester 100 may suffer from numerous disadvantages. For example, the multi-stage pump 110 may occupy 4 to 5 times as much area as a single stage pump. The multi-stage pump 110 may also be incapable of providing a variety of voltages. For example, a multi-stage pump 110 that is designed to supply 11 Volts may be capable of supplying voltages ranging from 0 Volts to 10 Volts from the memory pad 130 to the semiconductor memory array 140 through the transistor 145. For another example, a multi-stage pump 110 that is designed to supply 11 Volts may not be capable of supplying about 12 Volts to the transistor 145. Thus, the multi-stage pump 110 may not be useful if the semiconductor memory array 140 may preferably be tested using a larger voltage of about 12 Volts.
For another example, the multi-stage pump 110 may be driven by the clock generator 115. Because the multi-stage pump 110 includes a plurality of multiplying stages, each of which must be driven by a signal from the clock generator 115, the clock generator 115 may be undesirably large and may occupy an undesirably large area of the semiconductor memory device 105. The clock generator 115 may also require a driving signal from the oscillator 120 that may be provided in response to a signal provided by the enable logic 125.
Furthermore, when the semiconductor memory array 140 is in deep-power-down status, the current in the semiconductor memory device 105 may be very low. However, if the multi-stage pump 110, the clock generator 115, the oscillator 120, and the enable logic 125 are coupled to pad 160, which may provide the supply voltage from an external source to the semiconductor memory array 140, the noise current in these components may be much larger than the current in the semiconductor memory array 140. In that case, it may not be possible to measure the current that may be in the semiconductor memory array 140 during the deep-power-down mode.